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Marek, T., Pluháček, A. 2006 Reduction of Integer Multiplication Latency and Power Consumption Using Value Reuse, detail

Marek, T., Pluháček, A. 2006 Use of Speculative Computation for Arithmetic Accelerating, detail

Marek, T., Pluháček, A. 2005 Multiplier Execution Latency Reduction Using Variable Latency Pipeline, detail

Marek, T., Novotný, M., Crha, L. 2004 Design and Implementation of the Memory Scheduler for the PC-Based Router, detail