Languages for simulation and synthesis

Semestr: Winter

Range: 2+2s


Credits: 4

Programme type: Undefined

Study form: Fulltime

Course language:


The aim of this course is to familiarize the students with simulating digital circuits. General principles and possible strategies for simulation of circuits are mentioned as well. The main stress is put on teaching the languages VHDL and VERILOG which are also used for digital circuits synthesis.


Synchronous and asynchronous simulation, types of delays, signals, variables, delta delay, entity, architecture, process, sensitivity list, resolution function, data-flow statements, signal attributes, components, configuration.

Course syllabus:

1. Basic notions and principles of simulation technics, abstract levels of digital circuit description.
2. Domain of simulation values, synchronous and asynchronous simulation, simulation of structures and delays, introduction to VHDL.
3. Entities, architectures, review of data types and associated operations.
4. Special data types, mathematical libraries, conversions, operations, and resolution functions.
5. Sequential environment: processes, types of sequential statements, modeling combinatorial and sequential circuits.
6. Signals and their attributes. Modeling finite-state machines. Procedures and functions.
7. Parallel environment: data-flow description, types of parallel statements, modeling combinatorial and sequential circuits. Structural description, component configuration and instantiation.
8. Creating testbenches, configuration of structural architectures.
9. Parallel environment: blocks, guarded blocks, guarded statements, guarded signals, disconnecting drivers.
10. VHDL constructs for the synthesis.
11. Introduction to VERILOG, VERILOG & VHDL analogy.
12. Data types, operations, resolution function, modeling structures.
13. Modeling behavior of combinatorial and sequential circuits.
14. VERILOG constructs for the synthesis.

Seminar syllabus:

1. Introduction to seminars, familiarizing the ModelSim environment.
2. One-level entity and architecture declaration, generation of simple signals.
3. Models of combinatioral circuits, flip-flops and latches of various types.
4. Using mathematical libraries, demonstration of the resolution function.
5. Functional models of more complex circuits in sequential environment.
6. Project elaboration.
7. Project elaboration.
8. Creating structural models of digital circuits.
9. Project elaboration.
10. project elaboration.
11. Testing the project.
12. Modeling combinatorial circuits with VERILOG.
13. Modeling sequential circuits with VERILOG.
14. Assessment


1. Douša J.: Jazyk VHDL, skriptum ČVUT 2003,
2. Sjoholm S., Lindh L.: VHDL for Designers, Prentice Hall 1997
3. Dewey A.M.: Analysis and Design of Digital Systems with VHDL, PWS Publishing Company, Boston 1997
4. Ciletti M., D.: Starter's guide to VERILOG 2001, Prentice Hall 2003.