RLS Lattice for Virtex FPGA Using 32-bit and 20-bit Logaritmic Arithmic

Kadlec, J., Albu, F., Softley, C., Matoušek, R., Heřmánek, A., Coleman, J.N., Fagan, A.

KADLEC, J., et al. RLS Lattice for Virtex FPGA Using 32-bit and 20-bit Logaritmic Arithmic. [Research Report] Praha: AV ČR, Ústav teorie informace a automatizace, 2001. Report no. 2036.