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Fišer, P., Hlavička, J., Kubátová, H. 2003 Coverage-Directed Assignment Approach to BIST, detail

Fišer, P., Hlavička, J., Kubátová, H. 2003 CD-A Based BIST Method, detail

Herout, P., Racek, S., Hlavička, J. 2003 A Method of Functional Verification of Reliable Embedded Computer System, detail

Fišer, P., Hlavička, J., Kubátová, H. 2003 Column-Matching BIST Exploiting Test Don't-Cares, detail

Fišer, P., Hlavička, J., Kubátová, H. 2003 FC-Min: A Fast Multi-Output Boolean Minimizer, detail

Fišer, P., Hlavička, J. 2003 BOOM - A Heuristic Boolean Minimizer, detail

Kubátová, H., Hlavička, J., Racek, S., Kolář, J. 2003 Fault Injection for Time Triggered Architecture (FIT), detail

Fišer, P., Hlavička, J. 2003 A Flexible Minimization and Partitioning Method, detail

Herout, P., Racek, S., Hlavička, J. 2002 Model-Based Dependability Evaluation Method for TTP/C Based Systems, detail

Hlavička, J., Racek, S.R. 2002 C-Sim - The C Language Enhancement for Discrete-Time Simulation, detail

Náplava, P., Hlavička, J., Jelínek, I. 2002 Annual Report 2001, detail

Straube, B., Marinissen, E., Kotásek, Z., Novák, O., Hlavička, J., Růžička, R. 2002 Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002, detail

Fišer, P., Hlavička, J. 2002 A Set of Logic Design Benchmarks, detail

Ademaj, A., Grillinger, P., Herout, P., Hlavička, J. 2002 Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods, detail

ElShafey, K., Hlavička, J. 2002 Estimating the Amount of Spare CLBs for Reconfiguring FPGA, detail

Fišer, P., Hlavička, J. 2002 A Flexible Minimization and Partitioning Method, detail

ElShafey, K., Hlavička, J. 2002 On-Line Detection and Location of Faulty CLBs in FPGA-Based Systems, detail

Hlavička, J., Fišer, P. 2002 Minimization and Partitioning Method Reducing Input Sets, detail

Fišer, P., Hlavička, J. 2002 Column-Matching Based BIST Design Method, detail

Hlavička, J. 2001 Priority rozvoje informační společnosti v ČR, detail

Hlavička, J., Renovell, M., Pataricza, A., Sziray, J., Benyó, B. 2001 Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, detail

Fišer, P., Hlavička, J. 2001 Implicant Expansion Methods Used in the Boom Minimizer, detail

Hlavička, J., Fišer, P. 2001 A Heuristic Method of Two-Level Logic Synthesis, detail

Náplava, P., Hlavička, J., Jelínek, I. 2001 Annual Report 2000, detail

Hlavička, J., Racek, S., Herout, P. 2001 Modeling a Fault-Tolerant Distributed System, detail

Fišer, P., Hlavička, J. 2001 On the Use of Mutations in Boolean Minimization, detail

Kotásek, Z., Růžička, R., Strnadel, J., Hlavička, J. 2001 Interactive Tool for Behavioral Level Testability Analysis, detail

Bečvář, M., Daněk, M., ElShafey, K., Hlavička, J., Schmidt, J. 2001 Architecture Acceleration using FPGAs, detail

Hlavička, J., Fišer, P. 2001 BOOM - a Heuristic Boolean Minimizer, detail

ElShafey, K., Schmidt, J., Hlavička, J. 2001 Design and Analysis of a Suitable Serial Approach to CORDIC Magnitude Processor in an FPGA, detail

Fišer, P., Hlavička, J. 2001 BOOM - a Boolean Minimizer, detail

ElShafey, K., Hlavička, J., Schmidt, J. 2001 A Comparison of Serial and Parallel Approaches to FPGA Implementations of Arithmetic Functions, detail

ElShafey, K., Hlavička, J. 2001 An On-Line Self-Checking Approach for Testing FPGA Logic Blocks, detail

ElShafey, K., Hlavička, J. 2001 An Approach for Testing FPGA Logic Blocks, detail

Hlavička, J. 2000 Built-in Self-Test in Circuits with more than 10 Million Transistors, detail

Náplava, P., Hlavička, J., Jelínek, I. 2000 Annual Report 1999, detail

Hlavička, J., Schmidt, J. 2000 Programovatelné logické obvody, detail

Hlavička, J. 2000 Testování programovatelných hradlových polí I, detail

Hlavička, J. 2000 Testování programovatelných hradlových polí II, detail

Hlavička, J., Kadlec, J. 2000 Vstup českých institucí do evropské informační společnosti, detail

Hlavička, J., Racek, S., Herout, P. 2000 Evaluation of Process Controller Fault Tolerance using Simulation, detail

Hlavička, J., Kadlec, J. 2000 Vstup do evropské informační společnosti - program IST, detail

Fišer, P., Hlavička, J. 2000 Efficient Minimization Method for Incompletely Defined Boolean Functions, detail

Kotásek, Z., Růžička, R., Hlavička, J. 2000 Formal Approach to the RTL Testability Analysis, detail

Vais, V., Racek, S., Hlavička, J. 2000 Dependability Model of a Distributed Authentication System, detail

Novák, O., Hlavička, J. 2000 An Efficient Deterministic Test Pattern Compaction Scheme using Modified IC Scan Chain, detail

Hlavička, J., Fišer, P. 2000 Algorithm for Minimization of Partial Boolean Functions, detail

Květoň, K., Hlavička, J., Maruna, Z., Dubnová, M. 1999 Koncepce národní informační politiky ve vysokoškolském vzdělávání, detail

Hlavička, J., Herout, P., Racek, S. 1999 Simulační ověření funkce spolehlivého průmyslového mikropočítače, detail

Hlavička, J. 1999 On the Representativenes of ISCAS Benchmarks, detail

Hlavička, J., Květoň, K. 1999 Contributions of UNESCO to the Building of Future Information Society, detail

Hlavička, J. 1999 Fault injection as a tool for FT process controller design, detail

Hlavička, J., Racek, S., Herout, P. 1999 C-Sim v.4.1, detail

Hlavička, J., Macek, T., Kolář, J., Mannová, B., Williams, B. 1999 International Dimension of Virtual University, detail

Vais, V., Racek, S., Hlavička, J. 1999 Reliability Analysis of an Authentication Process, detail

Květoň, K., Hlavička, J. 1999 Contributions of UNESCO to the Building of Future Information Society, detail

Hlavička, J., Maehle, E., Pataricza, A. 1999 Dependable Computing - EDCC-3, detail

Květoň, K., Hlavička, J. 1998 Strategy for Transition to the Information Society in the Czech Republic, detail

Hlavička, J. 1998 Bezpečnost komerčního využití Internetu, detail

Hlavička, J., Racek, S., Herout, P. 1998 Analysis and Testing of Process Controller Dependability, detail

Novák, O., Hlavička, J. 1998 Design of a Cellular Automaton for Efficient Test Pattern Generation, detail

Hlavička, J. 1998 The Challenge of RUFIS'97, detail

Racek, S., Herout, P., Hlavička, J. 1998 Fault Injection as a Tool for FT Process Controller Design, detail

Hlavička, J. 1998 Bezpečnost informačních systémů, detail

Hlavička, J. 1998 Diagnostika a spolehlivost, detail

Květoň, K., Hlavička, J. 1998 Strategy for Transition to the Information Society in the Czech Republic, detail

Hlavička, J. 1998 Architektura počítačů, detail

Hlavička, J., Novák, O. 1998 Methods of Pseudoexhaustive Test Pattern Generation, detail

Kotásek, Z., Zbořil, F., Hlavička, J. 1997 Test Overhead Reduction through RT Level Testability Analysis, detail

Hlavička, J., Novák, O. 1997 Built-in Self-Test Equipment: State of the Art, detail

Blatný, J., Kotásek, Z., Hlavička, J. 1997 RT Level Test Scheduling, detail

Hlavička, J., Květoň, K. 1997 RUFIS '97. Proceedings for International Part of the Conference, detail

Hlavička, J. 1997 Computer Architecture, detail

Hlavička, J., Racek, S., Šmrha, P. 1996 Functional Validation of Fault-Tolerant Asynchronous Algorithms, detail

Hlavička, J. 1996 Architektura počítačů, detail

Hlavička, J., Novák, O. 1996 Enhancing Pseudoexhaustive Test Set Quality by Code Bit Inversions, detail

Hlavička, J., Racek, S. 1996 Multiprocesorové systémy, detail

Hlavička, J. 1996 Pseudoexhaustive Test Set Generator with Code Bit Inversions, detail

Zorian, Y., Hlavička, J. 1996 East Meets West, detail

Hlavička, J. 1995 Vývojové tendence superpočítačů, detail

Hlavička, J. 1995 Design and Test as Twin Disciplines, detail

Novák, O., Hlavička, J. 1995 Enhancing Fault Coverage of Pseudoexhaustive Test Sets, detail

Kotásek, Z., Kotásek, P., Hlavička, J. 1995 RT Level Test Scheduling Procedure, detail

Hlavička, J. 1994 Disková pole, detail

Hlavička, J. 1994 Future Directions in Dependable Computing - Position Paper, detail

Blatný, J., Kotásek, Z., Hlavička, J. 1993 I - Path Analysis, detail

Blatný, J., Kotásek, Z., Hlavička, J. 1993 RT Level Scheduling, detail