People

ING. MARTIN DANĚK, PH.D.

Buryan, P. 2014 Refinement Action-Based Framework for Utilization of Softcomputing in Inductive Learning, detail

Zemanová, M. 2012 Exploiting Ontologies and Higher Order Knowledge in Relational Data Mining, detail

Karel, F. 2009 Quantitative Association Rules Mining, detail

Daněk, M., Honzík, P., Kadlec, J., Matoušek, R., Pohl, Z. 2006 Platforma s částečnou dynamickou rekonfigurací FPGA, detail

Matoušek, R., Daněk, M., Kubátová, H. 2006 Perspektivy dynamické rekonfigurace programovatelných polí FPGA, detail

Daněk, M., Heřmánek, A., Honzík, P., Kadlec, J., Matoušek, R., Pohl, Z. 2005 GIN - Notetaker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs, detail

Daněk, M., Bartosinski, R., Honzík, P., Matoušek, R. 2005 Dynamic Reconfiguration in FPGA-Based SoC Designs, detail

Daněk, M., Kolář, J. 2004 FPGA Modelling for High-Performance Algorithms, detail

Daněk, M., Honzík, P., Kadlec, J., Matoušek, R., Pohl, Z. 2004 Reconfigurable System-on-a-Programmeable-Chip Platform, detail

Kuneš, M., Kubátová, H., Daněk, M. 2004 Partitioning Problem in HW/SW Codesign, detail

Daněk, M. 2004 Timing-Driven Physical Design for FPGAs, detail

Daněk, M., Kubátová, H., Kuneš, M. 2003 VLSI Group: Annual Report 2002, detail

Daněk, M., Kubátová, H., Muzikář, Z. 2003 Evolutionary Techniques in Physical Design for FPGAs, detail

Kuneš, M., Daněk, M. 2003 Invariant Modifications for Generation of Benchmark Circuits, detail

Matoušek, R., Daněk, M., Pohl, Z., Kadlec, J. 2003 Dynamic Runtime Parical Reconfiguration in FPGA, detail

Daněk, M., Kubátová, H., Muzikář, Z. 2003 Evolutionary Techniques in Physical Design for FPGAs, detail

Daněk, M., Kuneš, M. 2003 Invar - A Benchmark Generation Tool, detail

Kuneš, M., Daněk, M. 2003 Invar - a New Approach to EDA Benchmark Generation, detail

Daněk, M. 2003 Integrated iterative approach to FPGA placement, detail

Daněk, M., Muzikář, Z. 2002 Integrated Iterative Approach to FPGA Placement, detail

Daněk, M., Muzikář, Z. 2002 Integrated Timing-Driven Approach to the FPGA Layout, detail

Daněk, M., Muzikář, Z. 2002 Integrated Timing-Driven Approach to the FPGA Layout, detail

Daněk, M. 2002 Using a Classifier System for Technology Mapping for FPGAs, detail

Daněk, M. 2002 Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs, detail

Daněk, M., Smith, R.E. 2002 XCS Applied to Mapping FPGA Architectures, detail

Daněk, M. 2001 Adaptive Mapping for LUT-based FPGAs, detail

Wright, W.A., Smith, R.E., Daněk, M., Greenway, P. 2001 A Generalisable Measure of Self-Organisation and Emergence, detail

Daněk, M. 2001 Timing-driven Adaptive Mapper for LUT-based FPGAs, detail

Bečvář, M., Daněk, M., ElShafey, K., Hlavička, J., Schmidt, J. 2001 Architecture Acceleration using FPGAs, detail

Muzikář, Z., Daněk, M. 2000 Physical Design for FPGAs, detail

Wright, W.A., Smith, R.E., Daněk, M., Greenway, P. 2000 A Measure of Emergence in an Adapting, Multi-Agent Context, detail

Daněk, M. 1999 Global Routing Model, detail

Daněk, M., Muzikář, Z. 1999 Global Routing Models, detail

Schmidt, J., Daněk, M., Muzikář, Z. 1999 Copernicus COPRODES - Project Results, detail

Daněk, M., Servít, M. 1998 Experience with a Global Model Usage for Layout of FPGAs, detail

Jiřina, M. 1998 Initial Setting of Weights in the Kohonen Maps, detail

Daněk, M., Servít, M. 1997 XILINX XC4000 Global Routing Model, detail

Rozinek, J. 1996 Predikce časových řad neuronovými sítěmi, detail